The present invention relates to the field of integrated circuits, and more particularly to structures that protect CMOS logic from substrate carrier injection caused by the inductive switching of a power device.
The quest for increased profits and product performance is driving the electronics industry to seek more cost effective methods of fabricating electronic devices. One method of reducing cost is through integrating a variety of electronic devices onto a single semiconductor chip. In the past, electronic systems were created using discrete electronic circuits supported by a Printed Circuit Board (PCB). It is possible to fabricate these PCB based systems having discrete electronic circuits and devices onto a single Integrated Circuit (IC). Through reducing the number of discrete electronic components in an electronic system with an IC, it is possible to greatly reduce the cost of electronic systems. Replacing PCB based electronic systems has numerous other advantages besides cost. These other advantages include reductions in size, reductions in power consumption, and increases in reliability and device speed.
The integration and fabrication of electronic systems having a diverse array of devices onto a single IC presents several problems. In a perfect IC, all of the devices on the IC would only communicate and interact with each other through the interconnect wires fabricated on the IC. However, in reality, all of the devices on the IC are able to communicate and interact with each other through means other than the interconnect wires. When electronic systems are fabricated on a single IC, the IC substrate electrically couples all the devices in the electronic system together. The substrate electrically acts as a resistor that interconnects all of the devices fabricated on the IC. As a result, the various devices supported on the IC are able to interact with each other through the substrate.
Commonly, an IC will support both CMOS logic and one or more power MOSFET transistors. In this electronic system, the CMOS logic is used to control the operation of the power MOSFET, which operates an external device. These types of circuits are commonly used in automotive applications. Examples of external devices operated by the power MOSFET include power car windows, air bag deployments, dash board gauges, and various car light bulbs.
The interaction of the various devices supported on a single IC creates a carrier injection problem. As noted above, these ICs having power MOSFETs and CMOS arrays are connected to external devices. These external devices can include inductive elements, the most basic of which is the car light bulb. When the power MOSFET driving the external device is in an ON mode, current flows through the power MOSFET on the IC to the external device. However, when the power MOSFET is switched OFF, the stoppage of current creates a back EMF in the inductive element of the external device. As a result, the back EMF causes a reverse current that places a negative bias across the drain of the power MOSFET and the substrate of the IC. Consequently, there is an injection of carriers into the substrate. This injection of carriers into the substrate causes significant problems within the IC.
To further specify the problem, the drain of the power MOSFET and the substrate form a PN junction, a simple diode. When the back EMF in the inductive element causes a reversal in current through the inductor, a negative bias is placed across the N portion of the PN diode placing the diode in a forward bias mode. This negative bias causes the PN junction to inject carriers into the IC substrate. The presence of these carriers injected into the substrate causes several problems for the devices on the IC.
One of these problems is device latch-up. Latch-up is a phenomena where digital CMOS circuits become xe2x80x9cstuckxe2x80x9d in a specific logic state. Simply stated, latch-up is caused by an internal feedback mechanism associated with parasitic PNPN-like action. In addition, latch-up also causes a regenerative current that can permanently damage CMOS devices. When integrating CMOS devices with power MOSFETS on an IC, latch-up avoidance is an important goal.
Another problem associated with the integration of various devices onto a single IC is potential threshold shifts in PMOS and NMOS devices due to the body effect. Shifts in threshold voltage are a significant problem for CMOS logic, and analog CMOS devices in particular.
One solution to this problem of substrate carrier injection caused by the inductive switching of a power device is to simply put enough space between the CMOS logic and the power MOSFET such that the injected current is attenuated by the resistivity of the substrate prior to reaching the CMOS array. Through putting enough chip space between the CMOS logic and the power MOSFET, the effect of the injected carriers on the CMOS logic is reduced to a manageable level. Spacings on the order of 500 um spacing between the CMOS logic and power MOSFET are necessary to implement this solution. The problem with this solution is that the spacing consumes a large amount of chip space, making it expensive and undesirable.
Electric circuits that consume large amounts of chip area are more expensive and less efficient than electric circuits that use a smaller amount of chip area. First, the less chip area used by a circuit enables the chip to support more circuits and functions. Also, the smaller the area occupied by the circuit enables the fabrication of smaller chips and more chips on a wafer. Through increasing the number of chips per wafer, the cost of each chip is reduced. Therefore, it is highly desirable to reduce the size of the combined power MOSFET and CMOS logic circuit on the IC in order to reduce the amount of chip space consumed to increase wafer profitability.
The reduction in scale of ICs to meet modern demands and economics has reduced the distance between the power MOSFET and the CMOS logic array from hundreds to tens of micrometers. This reduction in scale greatly increases the impact that injected carriers from inductive switching has on the CMOS logic performance. It is therefore necessary to develop technology that can facilitate the continued reduction in scale of IC circuits while compensating for the problem of injected carriers from inductive switching.
It is therefore highly desirable to develop a structure that can shield CMOS logic from carrier injection caused by inductive feedback. It is highly desirable to develop an injection protection structure that uses a minimal amount of chip space in order to maximize the capabilities of the chip and enhance the chip cost.